In nonvolatile semiconductor memory devices such as a NAND flash memory, a flat cell structure advantageous to miniaturization has been again attracting attention in recent years.
An advantage of the flat cell structure is that an inter-gate insulating layer and a control gate electrode do not intervene between floating gate electrodes arranged in a row direction in which the control gate electrode (word line) extends, and therefore do not limit half of the pitch (half pitch) of bit lines extending in a column direction.
However, in the flat cell structure, the area in which the floating gate electrodes and the control gate electrode face each other is small, and a sufficient coupling ratio is not easily obtained. If the half pitch is narrowed by the flat cell structure, there will be a problem known as inter-cell interference in which memory cells arranged in the row direction interfere with one another in read and write operations.